1. Field of the Invention
The present invention relates generally to switches and/or routers. More particularly, the present invention relates to methods and systems for high-speed parameter assignment schemes for routing packets in sharable memory module based switch system.
2. Description of Related Art
The design of high-performance packet switches is essential due to the exponential growth of data traffic in systems such as the Internet. Further, the increase in bursty data traffic in high-speed networks and Internets has been the cause for a higher demand in throughput performance of packet switches and routers. One main objective in switch design and memory allocation in the switch is to provide the best possible delay-throughput performance that can scale almost linearly as the switch grows in size and capacity. It is known in the art that sharing of memory resources among the input and output ports of the switch improves throughput performance of a packet switch under heavy traffic, particularly bursty traffic.
Due to the reduced packet rate loss rate and throughput performance, the shared-memory based switches are suited for handling the dynamically changing nature of bursty data traffic in high-speed packet networks and Internets. However, scalability of the shared-memory based switching systems has been restricted by high memory bandwidth requirements, segregation of memory space, and centralized control of switching functions that cause the performance of the switch to degrade as shared-memory based system increases in size.
The referenced shortcomings are not intended to be exhaustive, but rather are among many that tend to impair the effectiveness of previously known techniques for high speed switches; however, those mentioned here are sufficient to demonstrate that the methodologies appearing in the art have not been altogether satisfactory and that a significant need exists for the techniques described and claimed in this disclosure.